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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-20 17:10:30 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-20 18:40:14 +0100 |
| commit | f84c9d8e17fbbfa3c0f8b533475e10142e046556 (patch) | |
| tree | d4ac8588f723a8aaa515d09e9bac0bd4b398ec62 /passes/memory | |
| parent | f599c148c570910195d7181037033d9d3e5238a3 (diff) | |
| download | yosys-f84c9d8e17fbbfa3c0f8b533475e10142e046556.tar.gz yosys-f84c9d8e17fbbfa3c0f8b533475e10142e046556.tar.bz2 yosys-f84c9d8e17fbbfa3c0f8b533475e10142e046556.zip | |
memory_share: Fix SAT-based sharing for wide ports.
Fixes #3117.
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_share.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 9d82739aa..ceea725d8 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -416,7 +416,9 @@ struct MemoryShareWorker else this_addr.extend_u0(GetSize(last_addr)); - port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); + + port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)}); port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; |