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authorMarcelina Kościelnicka <mwk@0x04.net>2021-05-27 23:43:25 +0200
committerMarcelina Kościelnicka <mwk@0x04.net>2021-05-28 00:40:56 +0200
commitcbf6b719fe85ce8544f9bb0796711f3f45638862 (patch)
treee5123705ba397f310a10c133d02fd4360c42800d /passes/memory
parent055ba748bcf8c77bff15bda0de49c0b4b3722bba (diff)
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Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_bram.cc15
1 files changed, 1 insertions, 14 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index b70864766..c1476669d 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1052,6 +1052,7 @@ grow_read_ports:;
void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
{
log("Processing %s.%s:\n", log_id(mem.module), log_id(mem.memid));
+ mem.narrow();
bool cell_init = !mem.inits.empty();
@@ -1069,20 +1070,6 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log(" %s=%d", it.first.c_str(), it.second);
log("\n");
- for (auto &port : mem.rd_ports) {
- if (port.wide_log2) {
- log("Wide read ports are not supported, skipping.\n");
- return;
- }
- }
-
- for (auto &port : mem.wr_ports) {
- if (port.wide_log2) {
- log("Wide write ports are not supported, skipping.\n");
- return;
- }
- }
-
// This pass cannot deal with write port priority — we need to emulate it,
// if present. Since priority emulation will change the enable signals,
// which in turn may change enable grouping and mapping eligibility in