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author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 15:55:54 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 16:00:34 -0700 |
commit | b567f03c266b0c44d81a24dde2ed538f1db05d4e (patch) | |
tree | 60e52f1a3738d85e8c9d55058abfe17eac41859c /passes/memory | |
parent | a076052fe423e262e00e75756f5f1b24ea461783 (diff) | |
download | yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.tar.gz yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.tar.bz2 yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.zip |
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
Diffstat (limited to 'passes/memory')
0 files changed, 0 insertions, 0 deletions