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authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-08-03 14:28:10 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-08-03 15:04:10 +0200
commit8733e1923a0dd0de727dd791dc4bcbf194b56b29 (patch)
tree3f8b77ad5c8fa9f4c93e03965683273c911873cd /passes/memory
parentca8ad62696df129a83b77d0e6c2ca33f0c553bc7 (diff)
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memory_bram: Move init data swizzling before other swizzling.
Fixes #2907.
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_bram.cc36
1 files changed, 18 insertions, 18 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 31fd769b0..af8137ada 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -798,6 +798,24 @@ grow_read_ports:;
for (int j = 0; j < i; j++)
mem.emulate_priority(j, i);
+ // Swizzle the init data. Do this before changing mem.width, so that get_init_data works.
+ bool cell_init = !mem.inits.empty();
+ vector<Const> initdata;
+ if (cell_init) {
+ Const initparam = mem.get_init_data();
+ initdata.reserve(mem.size);
+ for (int i = 0; i < mem.size; i++) {
+ std::vector<State> val;
+ for (auto idx : shuffle_map) {
+ if (idx == -1)
+ val.push_back(State::Sx);
+ else
+ val.push_back(initparam[mem.width * i + idx]);
+ }
+ initdata.push_back(Const(val));
+ }
+ }
+
// Now the big swizzle.
mem.width = GetSize(shuffle_map);
@@ -837,24 +855,6 @@ grow_read_ports:;
port.srst_value = new_srst_value;
}
- // Swizzle the init data.
- bool cell_init = !mem.inits.empty();
- vector<Const> initdata;
- if (cell_init) {
- Const initparam = mem.get_init_data();
- initdata.reserve(mem.size);
- for (int i = 0; i < mem.size; i++) {
- std::vector<State> val;
- for (auto idx : shuffle_map) {
- if (idx == -1)
- val.push_back(State::Sx);
- else
- val.push_back(initparam[mem.width * i + idx]);
- }
- initdata.push_back(Const(val));
- }
- }
-
// prepare variant parameters
dict<IdString, Const> variant_params;