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| author | David Shah <dave@ds0.me> | 2019-07-02 16:47:54 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-09 18:46:39 +0100 |
| commit | 4b49c0201edc37d0d3edd906e2693d6284a1b0ba (patch) | |
| tree | f5e8f7388e7e36e4fa096758e0e831594c1cd74b /passes/memory | |
| parent | 7b298479d4a10ac20379955fa749e70560b72b7f (diff) | |
| download | yosys-4b49c0201edc37d0d3edd906e2693d6284a1b0ba.tar.gz yosys-4b49c0201edc37d0d3edd906e2693d6284a1b0ba.tar.bz2 yosys-4b49c0201edc37d0d3edd906e2693d6284a1b0ba.zip | |
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
memory_dff: Fix checking of feedback mux input when more than one mux
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_dff.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 5215cce44..32b97f27a 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -17,6 +17,7 @@ * */ +#include <algorithm> #include "kernel/yosys.h" #include "kernel/sigtools.h" @@ -183,12 +184,12 @@ struct MemoryDffWorker if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) { RTLIL::SigSpec en; - RTLIL::SigSpec check_q; + std::vector<RTLIL::SigSpec> check_q; do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); sig_data = sigmap(mux->getPort("\\Y")); en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); @@ -197,7 +198,8 @@ struct MemoryDffWorker if (sigbit_users_count[bit] > 1) goto skip_ff_after_read_merging; - if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) + if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && + std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) { disconnect_dff(sig_data); cell->setPort("\\CLK", clk_data); |