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author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /passes/memory/memory_unpack.cc | |
parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip |
Use C++11 final/override keywords.
Diffstat (limited to 'passes/memory/memory_unpack.cc')
-rw-r--r-- | passes/memory/memory_unpack.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 8d284edcd..d04d4ba7a 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module) struct MemoryUnpackPass : public Pass { MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass { log("$memwr cells. It is the counterpart to the memory_collect pass.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) |