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authorMarcelina Koƛcielnicka <mwk@0x04.net>2022-06-17 15:29:37 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2022-06-17 16:56:11 +0200
commitab3a9325c33b5b1b9de6971b6931ee12c3e3871c (patch)
tree4aa2adeb8ab6f0b2bbde1af94163bd1342f59853 /passes/memory/memory_map.cc
parentc23139fd98f018d4f73b34e220a23787f640d130 (diff)
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memory_map: Add -rom-only option.
Diffstat (limited to 'passes/memory/memory_map.cc')
-rw-r--r--passes/memory/memory_map.cc22
1 files changed, 18 insertions, 4 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 21c7a761e..ccfb8c94f 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -30,6 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MemoryMapWorker
{
bool attr_icase = false;
+ bool rom_only = false;
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
RTLIL::Design *design;
@@ -107,11 +108,8 @@ struct MemoryMapWorker
SigSpec init_data = mem.get_init_data();
- // delete unused memory cell
- if (mem.rd_ports.empty()) {
- mem.remove();
+ if (!mem.wr_ports.empty() && rom_only)
return;
- }
// check if attributes allow us to infer FFRAM for this memory
for (const auto &attr : attributes) {
@@ -143,6 +141,12 @@ struct MemoryMapWorker
}
}
+ // delete unused memory cell
+ if (mem.rd_ports.empty()) {
+ mem.remove();
+ return;
+ }
+
// all write ports must share the same clock
RTLIL::SigSpec refclock;
bool refclock_pol = false;
@@ -373,10 +377,14 @@ struct MemoryMapPass : public Pass {
log(" -iattr\n");
log(" for -attr, ignore case of <value>.\n");
log("\n");
+ log(" -rom-only\n");
+ log(" only perform conversion for ROMs (memories with no write ports).\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool attr_icase = false;
+ bool rom_only = false;
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
log_header(design, "Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n");
@@ -413,6 +421,11 @@ struct MemoryMapPass : public Pass {
attr_icase = true;
continue;
}
+ if (args[argidx] == "-rom-only")
+ {
+ rom_only = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -421,6 +434,7 @@ struct MemoryMapPass : public Pass {
MemoryMapWorker worker(design, mod);
worker.attr_icase = attr_icase;
worker.attributes = attributes;
+ worker.rom_only = rom_only;
worker.run();
}
}