diff options
author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
commit | 956ecd48f71417b514c194a833a49238049e00b0 (patch) | |
tree | 468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/memory/memory_map.cc | |
parent | 2d86563bb206748d6eef498eb27f7a004f20113d (diff) | |
download | yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.gz yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.bz2 yosys-956ecd48f71417b514c194a833a49238049e00b0.zip |
kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/memory/memory_map.cc')
-rw-r--r-- | passes/memory/memory_map.cc | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b17db372a..da0673c8f 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -81,15 +81,15 @@ struct MemoryMapWorker std::set<int> static_ports; std::map<int, RTLIL::SigSpec> static_cells_map; - int wr_ports = cell->parameters["\\WR_PORTS"].as_int(); - int rd_ports = cell->parameters["\\RD_PORTS"].as_int(); + int wr_ports = cell->parameters[ID::WR_PORTS].as_int(); + int rd_ports = cell->parameters[ID::RD_PORTS].as_int(); - int mem_size = cell->parameters["\\SIZE"].as_int(); - int mem_width = cell->parameters["\\WIDTH"].as_int(); - int mem_offset = cell->parameters["\\OFFSET"].as_int(); - int mem_abits = cell->parameters["\\ABITS"].as_int(); + int mem_size = cell->parameters[ID::SIZE].as_int(); + int mem_width = cell->parameters[ID::WIDTH].as_int(); + int mem_offset = cell->parameters[ID::OFFSET].as_int(); + int mem_abits = cell->parameters[ID::ABITS].as_int(); - SigSpec init_data = cell->getParam("\\INIT"); + SigSpec init_data = cell->getParam(ID::INIT); init_data.extend_u0(mem_size*mem_width, true); // delete unused memory cell @@ -99,22 +99,22 @@ struct MemoryMapWorker } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); - RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; - RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK); + RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY]; + RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE]; clocks_pol.bits.resize(wr_ports); clocks_en.bits.resize(wr_ports); RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -155,21 +155,21 @@ struct MemoryMapWorker } else { - RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff)); + c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; if (clocks_pol.bits.size() > 0) { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->setPort("\\CLK", clocks.extract(0, 1)); + c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]); + c->setPort(ID::CLK, clocks.extract(0, 1)); } else { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1); + c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->setPort("\\D", data_reg_in.back()); + c->setPort(ID::D, data_reg_in.back()); - std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i); if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); @@ -177,10 +177,10 @@ struct MemoryMapWorker SigSpec w_init = init_data.extract(i*mem_width, mem_width); if (!w_init.is_fully_undef()) - w_out->attributes["\\init"] = w_init.as_const(); + w_out->attributes[ID::init] = w_init.as_const(); data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->setPort("\\Q", data_reg_out.back()); + c->setPort(ID::Q, data_reg_out.back()); } } @@ -188,55 +188,55 @@ struct MemoryMapWorker int count_dff = 0, count_mux = 0, count_wrmux = 0; - for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) + for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits); if (mem_offset) rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr))); std::vector<RTLIL::SigSpec> rd_signals; - rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width)); - if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) + if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1) { RTLIL::Cell *dff_cell = nullptr; - if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1) { - dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); - dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - dff_cell->setPort("\\D", rd_addr); + dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff)); + dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits); + dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]); + dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1)); + dff_cell->setPort(ID::D, rd_addr); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - dff_cell->setPort("\\Q", RTLIL::SigSpec(w)); + dff_cell->setPort(ID::Q, RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else { - dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - dff_cell->setPort("\\Q", rd_signals.back()); + dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff)); + dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; + dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]); + dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1)); + dff_cell->setPort(ID::Q, rd_signals.back()); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - dff_cell->setPort("\\D", rd_signals.back()); + dff_cell->setPort(ID::D, rd_signals.back()); } - SigBit en_bit = cell->getPort("\\RD_EN").extract(i); + SigBit en_bit = cell->getPort(ID::RD_EN).extract(i); if (en_bit != State::S1) { SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i), - dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit); - dff_cell->setPort("\\D", new_d); + dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit); + dff_cell->setPort(ID::D, new_d); } } @@ -246,8 +246,8 @@ struct MemoryMapWorker for (size_t k = 0; k < rd_signals.size(); k++) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux)); + c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; c->setPort(ID::Y, rd_signals[k]); c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1)); count_mux++; @@ -275,11 +275,11 @@ struct MemoryMapWorker RTLIL::SigSpec sig = data_reg_out[i]; - for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width); if (mem_offset) wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr))); @@ -303,12 +303,12 @@ struct MemoryMapWorker if (wr_bit != State::S1) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and)); + c->parameters[ID::A_SIGNED] = RTLIL::Const(0); + c->parameters[ID::B_SIGNED] = RTLIL::Const(0); + c->parameters[ID::A_WIDTH] = RTLIL::Const(1); + c->parameters[ID::B_WIDTH] = RTLIL::Const(1); + c->parameters[ID::Y_WIDTH] = RTLIL::Const(1); c->setPort(ID::A, w); c->setPort(ID::B, wr_bit); @@ -316,8 +316,8 @@ struct MemoryMapWorker c->setPort(ID::Y, RTLIL::SigSpec(w)); } - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); - c->parameters["\\WIDTH"] = wr_width; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux)); + c->parameters[ID::WIDTH] = wr_width; c->setPort(ID::A, sig.extract(wr_offset, wr_width)); c->setPort(ID::B, wr_data.extract(wr_offset, wr_width)); c->setPort(ID::S, RTLIL::SigSpec(w)); @@ -343,7 +343,7 @@ struct MemoryMapWorker { std::vector<RTLIL::Cell*> cells; for (auto cell : module->selected_cells()) - if (cell->type == "$mem" && design->selected(module, cell)) + if (cell->type == ID($mem)) cells.push_back(cell); for (auto cell : cells) handle_cell(cell); |