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| author | Aman Goel <amangoel@umich.edu> | 2018-08-18 08:18:40 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-18 08:18:40 +0530 |
| commit | 61f002c908830d59e883d25668b731e7d12470d0 (patch) | |
| tree | 25174f7321f60e14ca6c144544f29971c40abe9b /passes/memory/memory_map.cc | |
| parent | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (diff) | |
| parent | e343f3e6d475984c21611474bffe7dcd8f599497 (diff) | |
| download | yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.gz yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.bz2 yosys-61f002c908830d59e883d25668b731e7d12470d0.zip | |
Merge pull request #3 from YosysHQ/master
Updates from official repo
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index bffeec857..a0b808e56 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -352,7 +352,7 @@ struct MemoryMapWorker struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -362,7 +362,7 @@ struct MemoryMapPass : public Pass { log("pass to word-wide DFFs and address decoders.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); for (auto mod : design->selected_modules()) |