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| author | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
|---|---|---|
| committer | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
| commit | db73f3c26b2768f93c7573b7c7d74b1cc7a0756d (patch) | |
| tree | 81696fd98770e519aea96fe3a6e40bcc3b3a4360 /passes/memory/memory_libmap.cc | |
| parent | e7e8e3b0f65ea1ebfcf04bffd0d9ba90f8e0d7fe (diff) | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| download | yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.gz yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.bz2 yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.zip | |
Merge branch 'master' of https://github.com/ALGCDG/yosys
Diffstat (limited to 'passes/memory/memory_libmap.cc')
| -rw-r--r-- | passes/memory/memory_libmap.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 898e0af85..9e147b0bf 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -837,7 +837,7 @@ void MemMapping::handle_priority() { if (!port2.priority_mask[p1idx]) continue; for (auto &cfg: cfgs) { - auto &p1cfg = cfg.rd_ports[p1idx]; + auto &p1cfg = cfg.wr_ports[p1idx]; auto &p2cfg = cfg.wr_ports[p2idx]; bool found = false; for (auto &pgi: p2cfg.def->wrprio) { @@ -1706,10 +1706,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons if (pdef.wrbe_separate) { cell->setPort(stringf("\\PORT_%s_WR_EN", name), State::S0); cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren); - cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); + if (cfg.def->width_mode != WidthMode::Single) + cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); - if (cfg.def->byte != 0) + if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } } |