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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
| commit | 136842b1ef18b850b518705ff3e6df3958f28e0c (patch) | |
| tree | abcdddaf53bafd5e34e9aa278ffbe3d001b60cc4 /passes/memory/memory_collect.cc | |
| parent | 705e520a527864dc32f1934bb4b2b94d75f8f0ec (diff) | |
| parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
| download | yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.gz yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.bz2 yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.zip | |
Merge branch 'master' into eddie/submod_po
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6acbce62f..9dcb3f024 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort("\\RD_EN", sig_rd_en); + // Copy attributes from RTLIL memory to $mem + for (auto attr : memory->attributes) + mem->attributes[attr.first] = attr.second; + for (auto c : memcells) module->remove(c); |