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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:04:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:04:11 -0800 |
| commit | 63b7a48fbc250dd16847eed95d5ce79417cd7d2f (patch) | |
| tree | d366dcfce81740a64724065f6aa1bbbf26ec56f6 /passes/hierarchy/clkpart.cc | |
| parent | 23ecf12bbf955b09d24868fa4ce1bf02b5aadef0 (diff) | |
| download | yosys-63b7a48fbc250dd16847eed95d5ce79417cd7d2f.tar.gz yosys-63b7a48fbc250dd16847eed95d5ce79417cd7d2f.tar.bz2 yosys-63b7a48fbc250dd16847eed95d5ce79417cd7d2f.zip | |
clkpart to analyse async flops too
Diffstat (limited to 'passes/hierarchy/clkpart.cc')
| -rw-r--r-- | passes/hierarchy/clkpart.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc index b79625540..15a5328b9 100644 --- a/passes/hierarchy/clkpart.cc +++ b/passes/hierarchy/clkpart.cc @@ -162,6 +162,14 @@ struct ClkPartPass : public Pass { key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec()); } else + if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_))) + { + bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)); + log_assert(!enable_mode); // TODO + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + } + else continue; unassigned_cells.erase(cell); |