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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
| commit | 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 (patch) | |
| tree | 900ad3764a73cb81396bcf0c0be1bc92c4df135d /passes/fsm | |
| parent | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (diff) | |
| download | yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.gz yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.bz2 yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.zip | |
Use State::S{0,1}
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 90c958912..80913fda8 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(and_sig); break; case 0: - cases_vector.append(RTLIL::SigSpec(1, 1)); + cases_vector.append(State::S1); break; default: log_abort(); @@ -150,7 +150,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } else if (cases_vector.size() == 1) { module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, State::S0)); } } |