diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
| commit | 88d5185596a0cc8319658463a31b20644d90dd6b (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /passes/fsm/fsm_map.cc | |
| parent | 282cc77604a9a855c303869321d4179790b0b64b (diff) | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.gz yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.bz2 yosys-88d5185596a0cc8319658463a31b20644d90dd6b.zip | |
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
Diffstat (limited to 'passes/fsm/fsm_map.cc')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 90c958912..80913fda8 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(and_sig); break; case 0: - cases_vector.append(RTLIL::SigSpec(1, 1)); + cases_vector.append(State::S1); break; default: log_abort(); @@ -150,7 +150,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } else if (cases_vector.size() == 1) { module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, State::S0)); } } |