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author | Clifford Wolf <clifford@clifford.at> | 2019-11-12 14:26:02 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-11-12 14:26:02 +0100 |
commit | 16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856 (patch) | |
tree | 1673ad40ddcb8265493f79c776535cff9d9c00c0 /passes/fsm/fsm_detect.cc | |
parent | e0ba78bdf2d65ace45be575de6a1cc43baae7f22 (diff) | |
download | yosys-16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856.tar.gz yosys-16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856.tar.bz2 yosys-16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856.zip |
Bugfix in fsm_detect
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/fsm/fsm_detect.cc')
-rw-r--r-- | passes/fsm/fsm_detect.cc | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 5ae991b28..61e6f8011 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -158,22 +158,24 @@ static void detect_fsm(RTLIL::Wire *wire) std::set<sig2driver_entry_t> cellport_list; sig2user.find(sig_q, cellport_list); + auto sig_q_bits = sig_q.to_sigbit_pool(); + for (auto &cellport : cellport_list) { RTLIL::Cell *cell = cellport.first; bool set_output = false, clr_output = false; - if (cell->type == "$ne") + if (cell->type.in("$ne", "$reduce_or", "$reduce_bool")) set_output = true; - if (cell->type == "$eq") + if (cell->type.in("$eq", "$logic_not", "$reduce_and")) clr_output = true; - if (!set_output && !clr_output) { - clr_output = true; + if (set_output || clr_output) { for (auto &port_it : cell->connections()) - if (port_it.first != "\\A" || port_it.first != "\\Y") - clr_output = false; + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { @@ -184,6 +186,7 @@ static void detect_fsm(RTLIL::Wire *wire) ce.set(sig, val); } } + next_cellport:; } SigSpec sig_y = sig_d, sig_undef; |