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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-24 20:19:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-24 20:19:08 +0200 |
| commit | 88d0829d65c298d1918e4e4c3a01a00cc58780ba (patch) | |
| tree | b088b8ea362308582fbbfe5edab34646eea76d36 /passes/extract | |
| parent | ad9bbcbf40451231178ccce67ab5aaff37da81da (diff) | |
| download | yosys-88d0829d65c298d1918e4e4c3a01a00cc58780ba.tar.gz yosys-88d0829d65c298d1918e4e4c3a01a00cc58780ba.tar.bz2 yosys-88d0829d65c298d1918e4e4c3a01a00cc58780ba.zip | |
Automatically run "proc" on extract map files
Diffstat (limited to 'passes/extract')
| -rw-r--r-- | passes/extract/extract.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index d25af324e..0c639aeda 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -521,6 +521,11 @@ struct ExtractPass : public Pass { map = new RTLIL::Design; Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); fclose(f); + + if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { + Pass::call(map, "proc"); + Pass::call(map, "opt_clean"); + } } std::map<std::string, RTLIL::Module*> needle_map, haystack_map; |