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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
| commit | 7fccad92f76ddeee653d5dfec17868e9766a683a (patch) | |
| tree | c85e80d5652780f3b543e5937f6e7c6a1d191778 /passes/extract | |
| parent | cd71c70b4f55c89cdcfd6da23ff5f2002cb7d49d (diff) | |
| download | yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.gz yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.bz2 yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.zip | |
Added more help messages
Diffstat (limited to 'passes/extract')
| -rw-r--r-- | passes/extract/extract.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index eab1a1693..db9afcc62 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -248,6 +248,8 @@ struct ExtractPass : public Pass { log("This pass operates on whole modules or selected cells from modules. Other\n"); log("selected entities (wires, etc.) are ignored.\n"); log("\n"); + log("See 'help techmap' for a pass that does the opposite thing.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { |