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authorEddie Hung <eddie@fpgeh.com>2020-04-02 09:51:32 -0700
committerEddie Hung <eddie@fpgeh.com>2020-04-02 09:51:32 -0700
commit956ecd48f71417b514c194a833a49238049e00b0 (patch)
tree468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/equiv/equiv_struct.cc
parent2d86563bb206748d6eef498eb27f7a004f20113d (diff)
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kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/equiv/equiv_struct.cc')
-rw-r--r--passes/equiv/equiv_struct.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index ba1fd1d26..1b7bf96a8 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -110,9 +110,9 @@ struct EquivStructWorker
module->connect(sig_b, sig_a);
}
- auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
+ auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b));
- cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
+ cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b);
}
@@ -126,7 +126,7 @@ struct EquivStructWorker
pool<IdString> cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
@@ -139,7 +139,7 @@ struct EquivStructWorker
}
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
@@ -316,7 +316,7 @@ struct EquivStructPass : public Pass {
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{
- pool<IdString> fwonly_cells({ "$equiv" });
+ pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false;
bool mode_fwd = false;
int max_iter = -1;