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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /passes/equiv/equiv_simple.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'passes/equiv/equiv_simple.cc')
| -rw-r--r-- | passes/equiv/equiv_simple.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index c2fab26f2..0e5348880 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -90,8 +90,8 @@ struct EquivSimpleWorker bool run_cell() { - SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit(); int ez_context = ez->frozen_literal(); if (satgen.model_undef) @@ -115,9 +115,9 @@ struct EquivSimpleWorker if (verbose) { log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell)); - log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y"))); + log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y))); } else { - log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y"))); + log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y))); } int step = max_seq; @@ -199,7 +199,7 @@ struct EquivSimpleWorker if (!ez->solve(ez_context)) { log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); - equiv_cell->setPort("\\B", equiv_cell->getPort("\\A")); + equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A)); ez->assume(ez->NOT(ez_context)); return true; } @@ -256,7 +256,7 @@ struct EquivSimpleWorker if (GetSize(equiv_cells) > 1) { SigSpec sig; for (auto c : equiv_cells) - sig.append(sigmap(c->getPort("\\Y"))); + sig.append(sigmap(c->getPort(ID::Y))); log(" Grouping SAT models for %s:\n", log_signal(sig)); } @@ -344,8 +344,8 @@ struct EquivSimplePass : public Pass { int unproven_cells_counter = 0; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) { - auto bit = sigmap(cell->getPort("\\Y").as_bit()); + if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) { + auto bit = sigmap(cell->getPort(ID::Y).as_bit()); auto bit_group = bit; if (!nogroup && bit_group.wire) bit_group.offset = 0; |