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| author | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:23:40 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:23:40 +0300 |
| commit | f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (patch) | |
| tree | 1718152be88e472605074eedc6b927c55fe7f454 /passes/equiv/equiv_simple.cc | |
| parent | 73d426bc879087ca522ca595a8ba921b647fae27 (diff) | |
| download | yosys-f6fe73b31f6e6d8966ad4ddae860b4d79133cce2.tar.gz yosys-f6fe73b31f6e6d8966ad4ddae860b4d79133cce2.tar.bz2 yosys-f6fe73b31f6e6d8966ad4ddae860b4d79133cce2.zip | |
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
Diffstat (limited to 'passes/equiv/equiv_simple.cc')
0 files changed, 0 insertions, 0 deletions