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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
| commit | 956ecd48f71417b514c194a833a49238049e00b0 (patch) | |
| tree | 468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/equiv/equiv_remove.cc | |
| parent | 2d86563bb206748d6eef498eb27f7a004f20113d (diff) | |
| download | yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.gz yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.bz2 yosys-956ecd48f71417b514c194a833a49238049e00b0.zip | |
kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/equiv/equiv_remove.cc')
| -rw-r--r-- | passes/equiv/equiv_remove.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index 2a78e5246..6daa112b5 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { + if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y))); module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A)); module->remove(cell); |