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| author | tklam <tklam@easylogic.hk> | 2018-09-26 17:57:39 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-09-26 17:57:39 +0800 |
| commit | b86eb3deef7d80fc5450379c80047636832ef458 (patch) | |
| tree | 5804a2c0c2b5c3703a5228cb8d1cd5edd1a91085 /passes/equiv/equiv_make.cc | |
| parent | 2b89074240b42648c6fad377156b19f21fb23fb8 (diff) | |
| download | yosys-b86eb3deef7d80fc5450379c80047636832ef458.tar.gz yosys-b86eb3deef7d80fc5450379c80047636832ef458.tar.bz2 yosys-b86eb3deef7d80fc5450379c80047636832ef458.zip | |
fix bug: pass by reference
Diffstat (limited to 'passes/equiv/equiv_make.cc')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 8590c820b..e74dab36f 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -404,7 +404,7 @@ struct EquivMakeWorker } } - bool check_signal_in_fanout(pool<Cell*> visited_cells, SigBit source_bit, SigBit target_bit) + bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit) { if (source_bit == target_bit) return true; |