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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:31:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:31:21 +0200 |
| commit | 65f91e51205fdd436c569c4795517160960ac700 (patch) | |
| tree | 866f50f10a644202612aecce5ca07e48dec35102 /passes/equiv/equiv_add.cc | |
| parent | 4718e65763854d9870bf9b88a7c1b1e78e10f05f (diff) | |
| download | yosys-65f91e51205fdd436c569c4795517160960ac700.tar.gz yosys-65f91e51205fdd436c569c4795517160960ac700.tar.bz2 yosys-65f91e51205fdd436c569c4795517160960ac700.zip | |
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
Diffstat (limited to 'passes/equiv/equiv_add.cc')
0 files changed, 0 insertions, 0 deletions