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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-15 16:16:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 4c6647a4693838978354183d5553717fa2d97a48 (patch) | |
| tree | 45d3a43a9eef1785b33b8bda2af416780424f9bd /passes/equiv/Makefile.inc | |
| parent | ec4bbb1444b24d36c03a6635738e34b652e5aa1b (diff) | |
| download | yosys-4c6647a4693838978354183d5553717fa2d97a48.tar.gz yosys-4c6647a4693838978354183d5553717fa2d97a48.tar.bz2 yosys-4c6647a4693838978354183d5553717fa2d97a48.zip | |
xaiger: always sort input/output bits by port id
redundant for normal design, but necessary for holes
Diffstat (limited to 'passes/equiv/Makefile.inc')
0 files changed, 0 insertions, 0 deletions