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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-27 07:40:40 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-27 08:00:00 +0000 |
| commit | e50e4ee285e8c3989cdf983640451aebd7e6e152 (patch) | |
| tree | 9f71de8a0a78a8df713008146cbef3a03bcb3450 /passes/cmds | |
| parent | b8365547e9ba1fb018ba66d519d6f02d6d7580a6 (diff) | |
| download | yosys-e50e4ee285e8c3989cdf983640451aebd7e6e152.tar.gz yosys-e50e4ee285e8c3989cdf983640451aebd7e6e152.tar.bz2 yosys-e50e4ee285e8c3989cdf983640451aebd7e6e152.zip | |
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
Co-Authored-By: whitequark <whitequark@whitequark.org>
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/printattrs.cc | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 78cf1eeff..7f86823e3 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -34,6 +34,16 @@ struct PrintAttrsPass : public Pass { log("\n"); log("\n"); } + + static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { + if (x.flags == RTLIL::CONST_FLAG_STRING) + log("%s(* %s=\"%s\" *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.decode_string().c_str()); + else if (x.flags == RTLIL::CONST_FLAG_NONE) + log("%s(* %s=%s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.as_string().c_str()); + else + log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx = 1; @@ -42,29 +52,26 @@ struct PrintAttrsPass : public Pass { unsigned int indent = 0; for (auto mod : design->selected_modules()) { - if (design->selected_whole_module(mod)) { log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(mod->name)); indent += 2; for (auto &it : mod->attributes) - log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); + log_const(it.first, it.second, indent); } for (auto cell : mod->selected_cells()) { log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(cell->name)); indent += 2; - for (auto &it : cell->attributes) { - log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); - } + for (auto &it : cell->attributes) + log_const(it.first, it.second, indent); indent -= 2; } for (auto wire : mod->selected_wires()) { log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(wire->name)); indent += 2; - for (auto &it : wire->attributes) { - log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); - } + for (auto &it : wire->attributes) + log_const(it.first, it.second, indent); indent -= 2; } |