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author | Clifford Wolf <clifford@clifford.at> | 2014-02-06 19:30:08 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-06 19:30:08 +0100 |
commit | d7d1c7baf8590169347976e70132ff6709452951 (patch) | |
tree | 20dac0cf95367a7f609cae022c350bca809fb29f /passes/cmds | |
parent | f2fdcef13d9f6325196e1c9b3b9932e03bc6229f (diff) | |
download | yosys-d7d1c7baf8590169347976e70132ff6709452951.tar.gz yosys-d7d1c7baf8590169347976e70132ff6709452951.tar.bz2 yosys-d7d1c7baf8590169347976e70132ff6709452951.zip |
Added support for %m selection op
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/select.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index f1c251ebc..99f9d31e1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -187,6 +187,14 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) } } +static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs) +{ + lhs.optimize(design); + for (auto &it : lhs.selected_members) + lhs.selected_modules.insert(it.first); + lhs.selected_members.clear(); +} + static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::Selection &rhs) { if (rhs.full_selection) { @@ -568,6 +576,11 @@ static void select_stmt(RTLIL::Design *design, std::string arg) log_cmd_error("Must have at least one element on the stack for operator %%s.\n"); select_op_submod(design, work_stack[work_stack.size()-1]); } else + if (arg == "%m") { + if (work_stack.size() < 1) + log_cmd_error("Must have at least one element on the stack for operator %%s.\n"); + select_op_fullmod(design, work_stack[work_stack.size()-1]); + } else if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%x.\n"); @@ -893,6 +906,9 @@ struct SelectPass : public Pass { log(" expand top set by adding all modules of instantiated cells in selected\n"); log(" modules\n"); log("\n"); + log(" %%m\n"); + log(" expand top set by selecting all modules that contain selected objects\n"); + log("\n"); log("Example: the following command selects all wires that are connected to a\n"); log("'GATE' input of a 'SWITCH' cell:\n"); log("\n"); |