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author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 19:27:23 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-02-21 19:27:23 +0100 |
commit | d55790909c3b4244889d092c8eae630c7efd1aee (patch) | |
tree | 13d0c03a36f1773b7832c5a1c372660572471fb1 /passes/cmds | |
parent | 3b97b612feb07529abd99f913edb70104d1f259a (diff) | |
download | yosys-d55790909c3b4244889d092c8eae630c7efd1aee.tar.gz yosys-d55790909c3b4244889d092c8eae630c7efd1aee.tar.bz2 yosys-d55790909c3b4244889d092c8eae630c7efd1aee.zip |
Hotfix for 4c82ddf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/setundef.cc | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index aea3165e4..f6949c820 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -238,20 +238,11 @@ struct SetundefPass : public Pass { { if (params_mode) { - for (auto *cell : module->cells()) - { - // Only modify selected cells. - if (!design->selected(module, it)) { - continue; - } - - for (auto ¶meter : cell->parameters) - { + for (auto *cell : module->selected_cells()) { + for (auto ¶meter : cell->parameters) { for (auto &bit : parameter.second.bits) { if (bit > RTLIL::State::S1) - { bit = worker.next_bit(); - } } } } |