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author | Clifford Wolf <clifford@clifford.at> | 2017-08-19 00:15:12 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-08-19 00:15:12 +0200 |
commit | d38a64b1cf361073a20a1e90c2fc6e56792c1237 (patch) | |
tree | 84c24d49919cc556d27ffe45e0e15b2e802b8640 /passes/cmds | |
parent | bbdf7d9c66359fa4210477fd998a534fc9900392 (diff) | |
download | yosys-d38a64b1cf361073a20a1e90c2fc6e56792c1237.tar.gz yosys-d38a64b1cf361073a20a1e90c2fc6e56792c1237.tar.bz2 yosys-d38a64b1cf361073a20a1e90c2fc6e56792c1237.zip |
More intuitive handling of "cd .." for singleton modules
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/select.cc | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index d2e1a2e2b..7d2f4262b 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1482,17 +1482,53 @@ struct CdPass : public Pass { log("\n"); log(" cd ..\n"); log("\n"); + log("Remove trailing substrings that start with '.' in current module name until\n"); + log("the name of a module in the current design is generated, then switch to that\n"); + log("module. Otherwise clear the current selection.\n"); + log("\n"); + log(" cd\n"); + log("\n"); log("This is just a shortcut for 'select -clear'.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - if (args.size() != 2) + if (args.size() != 1 && args.size() != 2) log_cmd_error("Invalid number of arguments.\n"); - if (args[1] == "..") { + if (args.size() == 1 || args[1] == "/") { + design->selection_stack.back() = RTLIL::Selection(true); + design->selected_active_module = std::string(); + return; + } + + if (args[1] == "..") + { + string modname = design->selected_active_module; + design->selection_stack.back() = RTLIL::Selection(true); design->selected_active_module = std::string(); + + while (1) + { + size_t pos = modname.rfind('.'); + + if (pos == string::npos) + break; + + modname = modname.substr(0, pos); + Module *mod = design->module(modname); + + if (mod == nullptr) + continue; + + design->selected_active_module = modname; + design->selection_stack.back() = RTLIL::Selection(); + select_filter_active_mod(design, design->selection_stack.back()); + design->selection_stack.back().optimize(design); + return; + } + return; } |