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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-22 13:02:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-22 13:02:48 +0100 |
| commit | d361d313e1e190f5d55508b2155ddd23230befc3 (patch) | |
| tree | 8cce15a48753405873ead2ecd2153a9ae300cbe8 /passes/cmds | |
| parent | e8307cefd9c67420bf176655096a72978720e9ad (diff) | |
| download | yosys-d361d313e1e190f5d55508b2155ddd23230befc3.tar.gz yosys-d361d313e1e190f5d55508b2155ddd23230befc3.tar.bz2 yosys-d361d313e1e190f5d55508b2155ddd23230befc3.zip | |
Added "check -assert" doc
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/check.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 17b15caa0..f2d5a1c53 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -44,6 +44,9 @@ struct CheckPass : public Pass { log("When called with -noinit then this command also checks for wires which have\n"); log("the 'init' attribute set.\n"); log("\n"); + log("When called with -assert then the command will produce an error if any\n"); + log("problems are found in the current design.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { |