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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-02 18:44:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-02 18:44:24 +0100 |
| commit | ced4d7b321f01571e6746d2a3ff21efa270795a1 (patch) | |
| tree | a16f23432bccfd2bb7f0d5996e0534d3c34d8362 /passes/cmds | |
| parent | c6b33f81eb458233be15e1f53882b3684449f3b7 (diff) | |
| download | yosys-ced4d7b321f01571e6746d2a3ff21efa270795a1.tar.gz yosys-ced4d7b321f01571e6746d2a3ff21efa270795a1.tar.bz2 yosys-ced4d7b321f01571e6746d2a3ff21efa270795a1.zip | |
Added support for module->connections to select %ci, %co and %x handling
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/select.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 137f8618a..5712a023e 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -272,6 +272,21 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); + for (auto &conn : mod->connections) + { + std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector(); + std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector(); + + for (size_t i = 0; i < conn_lhs.size(); i++) { + if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL) + continue; + if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && lhs.selected_members[mod->name].count(conn_lhs[i].wire->name) == 0) + lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--; + if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && lhs.selected_members[mod->name].count(conn_rhs[i].wire->name) == 0) + lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--; + } + } + for (auto &cell : mod->cells) for (auto &conn : cell.second->connections) { |