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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 22:36:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 22:36:34 +0100 |
| commit | c6ae9ebb7997548fdf7445f9fda64dc97f8e92f8 (patch) | |
| tree | d68074f24ff23c1a813c6b82a1f3d6dad7fc754e /passes/cmds | |
| parent | e9368a1d7e13bc691f86f25cd80981110b937cab (diff) | |
| download | yosys-c6ae9ebb7997548fdf7445f9fda64dc97f8e92f8.tar.gz yosys-c6ae9ebb7997548fdf7445f9fda64dc97f8e92f8.tar.bz2 yosys-c6ae9ebb7997548fdf7445f9fda64dc97f8e92f8.zip | |
Fixed "stat" handling of blackbox modules
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/stat.cc | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index d68c57b20..bd3a43aca 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -208,20 +208,17 @@ struct StatPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules_) + for (auto mod : design->selected_modules()) { - if (!design->selected_module(it.first)) - continue; - if (!top_mod && design->full_selection()) - if (it.second->get_bool_attribute("\\top")) - top_mod = it.second; + if (mod->get_bool_attribute("\\top")) + top_mod = mod; - statdata_t data(design, it.second, width_mode); - mod_stat[it.first] = data; + statdata_t data(design, mod, width_mode); + mod_stat[mod->name] = data; log("\n"); - log("=== %s%s ===\n", RTLIL::id2cstr(it.first), design->selected_whole_module(it.first) ? "" : " (partially selected)"); + log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("\n"); data.log_data(); } |