Added Yosys::{dict,nodict,vector} container types

5 files changed, 12 insertions, 12 deletions

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 8c3391e52..d7edcfbfc 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -91,10 +91,10 @@ struct DeletePass : public Pass {
 				continue;
 			}
 
-			std::set<RTLIL::Wire*> delete_wires;
-			std::set<RTLIL::Cell*> delete_cells;
-			std::set<RTLIL::IdString> delete_procs;
-			std::set<RTLIL::IdString> delete_mems;
+			nodict<RTLIL::Wire*> delete_wires;
+			nodict<RTLIL::Cell*> delete_cells;
+			nodict<RTLIL::IdString> delete_procs;
+			nodict<RTLIL::IdString> delete_mems;
 
 			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index b2e10e557..8f24af278 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -118,7 +118,7 @@ struct RenamePass : public Pass {
 				if (!design->selected(module))
 					continue;
 
-				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 				for (auto &it : module->wires_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -128,7 +128,7 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 				module->fixup_ports();
 
-				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -149,7 +149,7 @@ struct RenamePass : public Pass {
 				if (!design->selected(module))
 					continue;
 
-				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 				for (auto &it : module->wires_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\' && it.second->port_id == 0)
@@ -159,7 +159,7 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 				module->fixup_ports();
 
-				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\')
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 7f841673f..91368f572 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -101,7 +101,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char
 	log_abort();
 }
 
-static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
 {
 	if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
 		for (auto &it : attributes) {
@@ -119,7 +119,7 @@ static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes
 	return false;
 }
 
-static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
 {
 	size_t pos = match_expr.find_first_of("<!=>");
 
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 39c75c54e..9a6d8a038 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -50,7 +50,7 @@ struct setunset_t
 	}
 };
 
-static void do_setunset(std::map<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
+static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
 {
 	for (auto &item : list)
 		if (item.unset)
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index a6c9fe883..6c24a8e5f 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
 
 			module->rewrite_sigspecs(worker);
 
-			std::set<RTLIL::Wire*> delete_wires;
+			nodict<RTLIL::Wire*> delete_wires;
 			for (auto &it : worker.splitmap)
 				delete_wires.insert(it.first);
 			module->remove(delete_wires);