SigSpec refactoring: renamed chunks and width to __chunks and __width

10 files changed, 39 insertions, 39 deletions

diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index f99cb9b50..f8f9e0590 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 {
 	CellTypes ct(design);
 
-	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width);
+	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width);
 
 	for (auto &it : module->cells)
 	for (auto &port : it.second->connections)
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index dd8b4fede..426d2b624 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -90,7 +90,7 @@ struct ConnwrappersWorker
 					continue;
 
 				int inner_width = cell->parameters.at(decl.widthparam).as_int();
-				int outer_width = conn.second.width;
+				int outer_width = conn.second.__width;
 				bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool();
 
 				if (inner_width >= outer_width)
@@ -124,20 +124,20 @@ struct ConnwrappersWorker
 
 					int extend_width = 0;
 					RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0);
-					while (extend_width < extend_sig.width && i + extend_width + 1 < sigbits.size() &&
+					while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() &&
 							sigbits[i + extend_width + 1] == extend_bit) extend_width++;
 
 					if (extend_width == 0)
 						continue;
 
-					if (old_sig.width == 0)
+					if (old_sig.__width == 0)
 						old_sig = conn.second;
 
 					conn.second.replace(i+1, extend_sig.extract(0, extend_width));
 					i += extend_width;
 				}
 
-				if (old_sig.width)
+				if (old_sig.__width)
 					log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
 							RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
 			}
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index ce6ac4aff..16828e4fb 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -28,7 +28,7 @@ struct DeleteWireWorker
 
 	void operator()(RTLIL::SigSpec &sig) {
 		sig.optimize();
-		for (auto &c : sig.chunks)
+		for (auto &c : sig.__chunks)
 			if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
 				c.wire = module->addWire(NEW_ID, c.width);
 				c.offset = 0;
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index e5f78830e..da36c7821 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -53,7 +53,7 @@ struct ScatterPass : public Pass {
 			{
 				RTLIL::Wire *wire = new RTLIL::Wire;
 				wire->name = NEW_ID;
-				wire->width = p.second.width;
+				wire->width = p.second.__width;
 				mod_it.second->add(wire);
 
 				if (ct.cell_output(c.second->type, p.first)) {
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index f8c351a43..d668bc3a4 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -191,7 +191,7 @@ struct SccWorker
 			nextsig.sort_and_unify();
 			sig = prevsig.extract(nextsig);
 
-			for (auto &chunk : sig.chunks)
+			for (auto &chunk : sig.__chunks)
 				if (chunk.wire != NULL)
 					sel.selected_members[module->name].insert(chunk.wire->name);
 		}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 9ef60a28f..068162eb1 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		include_match:
 			is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first);
 			is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
-			for (auto &chunk : conn.second.chunks)
+			for (auto &chunk : conn.second.__chunks)
 				if (chunk.wire != NULL) {
 					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0)
 						if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 9d59834c2..3a99c0cec 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -48,7 +48,7 @@ struct SetundefWorker
 	void operator()(RTLIL::SigSpec &sig)
 	{
 		sig.expand();
-		for (auto &c : sig.chunks)
+		for (auto &c : sig.__chunks)
 			if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
 				c.data.bits.at(0) = next_bit();
 		sig.optimize();
@@ -141,7 +141,7 @@ struct SetundefPass : public Pass {
 						undriven_signals.del(sigmap(conn.second));
 
 				RTLIL::SigSpec sig = undriven_signals.export_all();
-				for (auto &c : sig.chunks) {
+				for (auto &c : sig.__chunks) {
 					RTLIL::SigSpec bits;
 					for (int i = 0; i < c.width; i++)
 						bits.append(next_bit());
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index eab42e6ff..0006a3ff4 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -78,7 +78,7 @@ struct ShowWorker
 	std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor)
 	{
 		sig.sort_and_unify();
-		for (auto &c : sig.chunks) {
+		for (auto &c : sig.__chunks) {
 			if (c.wire != NULL)
 				for (auto &s : color_selections)
 					if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
@@ -173,13 +173,13 @@ struct ShowWorker
 	{
 		sig.optimize();
 
-		if (sig.chunks.size() == 0) {
+		if (sig.__chunks.size() == 0) {
 			fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
 			return stringf("v%d", single_idx_count++);
 		}
 
-		if (sig.chunks.size() == 1) {
-			RTLIL::SigChunk &c = sig.chunks[0];
+		if (sig.__chunks.size() == 1) {
+			RTLIL::SigChunk &c = sig.__chunks[0];
 			if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
 				if (!range_check || c.wire->width == c.width)
 						return stringf("n%d", id2num(c.wire->name));
@@ -200,10 +200,10 @@ struct ShowWorker
 		{
 			std::string label_string;
 			sig.optimize();
-			int pos = sig.width-1;
+			int pos = sig.__width-1;
 			int idx = single_idx_count++;
-			for (int i = int(sig.chunks.size())-1; i >= 0; i--) {
-				RTLIL::SigChunk &c = sig.chunks[i];
+			for (int i = int(sig.__chunks.size())-1; i >= 0; i--) {
+				RTLIL::SigChunk &c = sig.__chunks[i];
 				net = gen_signode_simple(c, false);
 				assert(!net.empty());
 				if (driver) {
@@ -225,9 +225,9 @@ struct ShowWorker
 			if (!port.empty()) {
 				currentColor = xorshift32(currentColor);
 				if (driver)
-					code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.width).c_str());
+					code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.__width).c_str());
 				else
-					code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.width).c_str());
+					code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.__width).c_str());
 			}
 			if (node != NULL)
 				*node = stringf("x%d", idx);
@@ -239,7 +239,7 @@ struct ShowWorker
 					net_conn_map[net].in.insert(port);
 				else
 					net_conn_map[net].out.insert(port);
-				net_conn_map[net].bits = sig.width;
+				net_conn_map[net].bits = sig.__width;
 				net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
 			}
 			if (node != NULL)
@@ -405,7 +405,7 @@ struct ShowWorker
 				code += gen_portbox("", sig, false, &node);
 				fprintf(f, "%s", code.c_str());
 				net_conn_map[node].out.insert(stringf("p%d", pidx));
-				net_conn_map[node].bits = sig.width;
+				net_conn_map[node].bits = sig.__width;
 				net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
 			}
 
@@ -414,7 +414,7 @@ struct ShowWorker
 				code += gen_portbox("", sig, true, &node);
 				fprintf(f, "%s", code.c_str());
 				net_conn_map[node].in.insert(stringf("p%d", pidx));
-				net_conn_map[node].bits = sig.width;
+				net_conn_map[node].bits = sig.__width;
 				net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
 			}
 
@@ -427,12 +427,12 @@ struct ShowWorker
 		for (auto &conn : module->connections)
 		{
 			bool found_lhs_wire = false;
-			for (auto &c : conn.first.chunks) {
+			for (auto &c : conn.first.__chunks) {
 				if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
 					found_lhs_wire = true;
 			}
 			bool found_rhs_wire = false;
-			for (auto &c : conn.second.chunks) {
+			for (auto &c : conn.second.__chunks) {
 				if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
 					found_rhs_wire = true;
 			}
@@ -446,11 +446,11 @@ struct ShowWorker
 
 			if (left_node[0] == 'x' && right_node[0] == 'x') {
 				currentColor = xorshift32(currentColor);
-			fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.width).c_str());
+			fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.__width).c_str());
 		} else {
-				net_conn_map[right_node].bits = conn.first.width;
+				net_conn_map[right_node].bits = conn.first.__width;
 				net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color);
-				net_conn_map[left_node].bits = conn.first.width;
+				net_conn_map[left_node].bits = conn.first.__width;
 				net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color);
 				if (left_node[0] == 'x') {
 					net_conn_map[right_node].in.insert(left_node);
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index a48a54a12..80a7f90c0 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -52,7 +52,7 @@ struct SpliceWorker
 
 	RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig)
 	{
-		if (sig.width == 0 || sig.is_fully_const())
+		if (sig.__width == 0 || sig.is_fully_const())
 			return sig;
 
 		if (sliced_signals_cache.count(sig))
@@ -69,15 +69,15 @@ struct SpliceWorker
 
 		RTLIL::SigSpec new_sig = sig;
 
-		if (sig_a.width != sig.width) {
+		if (sig_a.__width != sig.__width) {
 			RTLIL::Cell *cell = new RTLIL::Cell;
 			cell->name = NEW_ID;
 			cell->type = "$slice";
 			cell->parameters["\\OFFSET"] = offset;
-			cell->parameters["\\A_WIDTH"] = sig_a.width;
-			cell->parameters["\\Y_WIDTH"] = sig.width;
+			cell->parameters["\\A_WIDTH"] = sig_a.__width;
+			cell->parameters["\\Y_WIDTH"] = sig.__width;
 			cell->connections["\\A"] = sig_a;
-			cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width);
+			cell->connections["\\Y"] = module->addWire(NEW_ID, sig.__width);
 			new_sig = cell->connections["\\Y"];
 			module->add(cell);
 		}
@@ -90,7 +90,7 @@ struct SpliceWorker
 
 	RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig)
 	{
-		if (sig.width == 0 || sig.is_fully_const())
+		if (sig.__width == 0 || sig.is_fully_const())
 			return sig;
 
 		if (spliced_signals_cache.count(sig))
@@ -134,11 +134,11 @@ struct SpliceWorker
 			RTLIL::Cell *cell = new RTLIL::Cell;
 			cell->name = NEW_ID;
 			cell->type = "$concat";
-			cell->parameters["\\A_WIDTH"] = new_sig.width;
-			cell->parameters["\\B_WIDTH"] = sig2.width;
+			cell->parameters["\\A_WIDTH"] = new_sig.__width;
+			cell->parameters["\\B_WIDTH"] = sig2.__width;
 			cell->connections["\\A"] = new_sig;
 			cell->connections["\\B"] = sig2;
-			cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width);
+			cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.__width + sig2.__width);
 			new_sig = cell->connections["\\Y"];
 			module->add(cell);
 		}
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 7e043bcff..7572baa35 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -63,7 +63,7 @@ struct SplitnetsWorker
 	void operator()(RTLIL::SigSpec &sig)
 	{
 		sig.expand();
-		for (auto &c : sig.chunks)
+		for (auto &c : sig.__chunks)
 			if (splitmap.count(c.wire) > 0)
 				c = splitmap.at(c.wire).at(c.offset);
 		sig.optimize();
@@ -144,7 +144,7 @@ struct SplitnetsPass : public Pass {
 						continue;
 
 					RTLIL::SigSpec sig = p.second.optimized();
-					for (auto &chunk : sig.chunks) {
+					for (auto &chunk : sig.__chunks) {
 						if (chunk.wire == NULL)
 							continue;
 						if (chunk.wire->port_id == 0 || flag_ports) {