Clean up `passes/cmds/connwrappers.cc`.

1 files changed, 7 insertions, 15 deletions

diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 5a15cbbaf..6ae7c9304 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -65,15 +65,13 @@ struct ConnwrappersWorker
 		decls[key] = decl;
 	}
 
-	void work(RTLIL::Design *design, RTLIL::Module *module)
+	void work(RTLIL::Module *module)
 	{
 		std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
 		SigMap sigmap(module);
 
-		for (auto &it : module->cells_)
+		for (auto cell : module->cells())
 		{
-			RTLIL::Cell *cell = it.second;
-
 			if (!decl_celltypes.count(cell->type))
 				continue;
 
@@ -105,13 +103,8 @@ struct ConnwrappersWorker
 			}
 		}
 
-		for (auto &it : module->cells_)
+		for (auto cell : module->selected_cells())
 		{
-			RTLIL::Cell *cell = it.second;
-
-			if (!design->selected(module, cell))
-				continue;
-
 			for (auto &conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
@@ -141,8 +134,8 @@ struct ConnwrappersWorker
 				}
 
 				if (old_sig.size())
-					log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
-							RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
+					log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name),
+							log_id(conn.first), log_signal(old_sig), log_signal(conn.second));
 			}
 		}
 	}
@@ -200,9 +193,8 @@ struct ConnwrappersPass : public Pass {
 
 		log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
 
-		for (auto &mod_it : design->modules_)
-			if (design->selected(mod_it.second))
-				worker.work(design, mod_it.second);
+		for (auto module : design->selected_modules())
+			worker.work(module);
 	}
 } ConnwrappersPass;