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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
| commit | 7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch) | |
| tree | 9c65e6929e43faec716efab17b37bd53f9afa4b3 /passes/cmds | |
| parent | 6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff) | |
| download | yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.gz yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.bz2 yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.zip | |
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/splice.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 4ce2ec11c..2556fb740 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -64,7 +64,7 @@ struct SpliceWorker return sliced_signals_cache.at(sig); int offset = 0; - int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1; + int p = driven_bits_map.at(sig.extract(0, 1).as_bit()) - 1; while (driven_bits.at(p) != RTLIL::State::Sm) p--, offset++; |