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author | Clifford Wolf <clifford@clifford.at> | 2014-02-16 17:39:50 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-16 17:39:50 +0100 |
commit | 42ce3db983fdb512e181daab1817991a661066ff (patch) | |
tree | 2aa8e4a5c3de0ab79679e44564731b6cbe0ee822 /passes/cmds | |
parent | d3dc22a90f8b87ffe0109b0fa2074d887642e7cb (diff) | |
download | yosys-42ce3db983fdb512e181daab1817991a661066ff.tar.gz yosys-42ce3db983fdb512e181daab1817991a661066ff.tar.bz2 yosys-42ce3db983fdb512e181daab1817991a661066ff.zip |
Fixed use of selection in splitnets command
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/splitnets.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index da9ef43f9..7e043bcff 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -169,7 +169,7 @@ struct SplitnetsPass : public Pass { { for (auto &w : module->wires) { RTLIL::Wire *wire = w.second; - if (wire->width > 1 && (wire->port_id == 0 || flag_ports)) + if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); } |