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author | Clifford Wolf <clifford@clifford.at> | 2014-02-08 00:06:00 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-08 00:06:00 +0100 |
commit | 2c51619c2b11edb63c147b1f6eea75c0b01e7256 (patch) | |
tree | 6d5f1a369f12a437b3f4f1e1bd26494bdde8ed09 /passes/cmds | |
parent | 274bcef66c4c70a15358e0c7b7e90aa8f8a668e6 (diff) | |
download | yosys-2c51619c2b11edb63c147b1f6eea75c0b01e7256.tar.gz yosys-2c51619c2b11edb63c147b1f6eea75c0b01e7256.tar.bz2 yosys-2c51619c2b11edb63c147b1f6eea75c0b01e7256.zip |
Now also move net labes to the right position in splice cmd
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/splice.cc | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index bfb27c383..a53a39197 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -186,7 +186,7 @@ struct SpliceWorker } } - std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_outputs; + std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires; for (auto &it : module->wires) if (it.second->port_output) { @@ -197,10 +197,17 @@ struct SpliceWorker continue; RTLIL::SigSpec new_sig = get_spliced_signal(sig); if (new_sig != sig) - rework_outputs.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, new_sig)); + rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, new_sig)); + } else + if (!it.second->port_input) { + RTLIL::SigSpec sig = sigmap(it.second); + if (spliced_signals_cache.count(sig) && spliced_signals_cache.at(sig) != sig) + rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, spliced_signals_cache.at(sig))); + else if (sliced_signals_cache.count(sig) && sliced_signals_cache.at(sig) != sig) + rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, sliced_signals_cache.at(sig))); } - for (auto &it : rework_outputs) + for (auto &it : rework_wires) { module->wires.erase(it.first->name); RTLIL::Wire *new_port = new RTLIL::Wire(*it.first); |