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author | whitequark <whitequark@whitequark.org> | 2020-11-02 06:33:03 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-11-03 12:37:02 +0000 |
commit | 191406f930ea27c10f08fe1abcbe954fc537dcba (patch) | |
tree | ffb6becce205f7db9ee27c5580fa798d7f437e11 /passes/cmds | |
parent | e7f36d01e44fb76b2352606ee6c7001662a7c638 (diff) | |
download | yosys-191406f930ea27c10f08fe1abcbe954fc537dcba.tar.gz yosys-191406f930ea27c10f08fe1abcbe954fc537dcba.tar.bz2 yosys-191406f930ea27c10f08fe1abcbe954fc537dcba.zip |
check: reformat log/help text to match most other passes
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/check.cc | 36 |
1 files changed, 17 insertions, 19 deletions
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index a8b5362b3..54b9b340d 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -35,30 +35,28 @@ struct CheckPass : public Pass { log("\n"); log("This pass identifies the following problems in the current design:\n"); log("\n"); - log(" - combinatorial loops\n"); - log("\n"); - log(" - two or more conflicting drivers for one wire\n"); - log("\n"); - log(" - used wires that do not have a driver\n"); + log(" - combinatorial loops\n"); + log(" - two or more conflicting drivers for one wire\n"); + log(" - used wires that do not have a driver\n"); log("\n"); log("Options:\n"); log("\n"); - log(" -noinit\n"); - log(" Also check for wires which have the 'init' attribute set.\n"); + log(" -noinit\n"); + log(" also check for wires which have the 'init' attribute set\n"); log("\n"); - log(" -initdrv\n"); - log(" Also check for wires that have the 'init' attribute set and are not\n"); - log(" driven by an FF cell type.\n"); + log(" -initdrv\n"); + log(" also check for wires that have the 'init' attribute set and are not\n"); + log(" driven by an FF cell type\n"); log("\n"); - log(" -mapped\n"); - log(" Also check for internal cells that have not been mapped to cells of the\n"); - log(" target architecture.\n"); + log(" -mapped\n"); + log(" also check for internal cells that have not been mapped to cells of the\n"); + log(" target architecture\n"); log("\n"); - log(" -allow-tbuf\n"); - log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n"); + log(" -allow-tbuf\n"); + log(" modify the -mapped behavior to still allow $_TBUF_ cells\n"); log("\n"); - log(" -assert\n"); - log(" Produce a runtime error if any problems are found in the current design.\n"); + log(" -assert\n"); + log(" produce a runtime error if any problems are found in the current design\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) override @@ -103,7 +101,7 @@ struct CheckPass : public Pass { if (module->has_processes_warn()) continue; - log("checking module %s..\n", log_id(module)); + log("Checking module %s...\n", log_id(module)); SigMap sigmap(module); dict<SigBit, vector<string>> wire_drivers; @@ -216,7 +214,7 @@ struct CheckPass : public Pass { } } - log("found and reported %d problems.\n", counter); + log("Found and reported %d problems.\n", counter); if (assert_mode && counter > 0) log_error("Found %d problems in 'check -assert'.\n", counter); |