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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-01 16:53:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-01 17:14:32 +0200 |
| commit | d13eb7e0999def2da03eb6ddef805145f7fd9c9a (patch) | |
| tree | d7634c448a42722357b474926056c10797f1546d /passes/cmds/trace.cc | |
| parent | 97a17d39e2f0088e02ed8496d905528722115674 (diff) | |
| download | yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.tar.gz yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.tar.bz2 yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.zip | |
Added ModIndex helper class, some changes to RTLIL::Monitor
Diffstat (limited to 'passes/cmds/trace.cc')
| -rw-r--r-- | passes/cmds/trace.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index b4bc45c20..6a5ea346e 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -34,9 +34,9 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - virtual void notify_cell_connect(RTLIL::Cell *cell, const std::pair<RTLIL::IdString, RTLIL::SigSpec> &conn) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override { - log("#TRACE# Cell connect: %s.%s.%s = %s\n", log_id(cell->module), log_id(cell), log_id(conn.first), log_signal(conn.second)); + log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override @@ -44,7 +44,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_new_connections(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override + virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) |