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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
| commit | f9946232adf887e5aa4a48c64f88eaa17e424009 (patch) | |
| tree | 39594b3287c3369752668456c4a6b1735fb66e77 /passes/cmds/splitnets.cc | |
| parent | d7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff) | |
| download | yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.gz yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.bz2 yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.zip | |
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'passes/cmds/splitnets.cc')
| -rw-r--r-- | passes/cmds/splitnets.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6bffba622..accb178ba 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -163,7 +163,7 @@ struct SplitnetsPass : public Pass { } else { - for (auto &w : module->wires) { + for (auto &w : module->wires_) { RTLIL::Wire *wire = w.second; if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); |