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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:42:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:45:47 +0200 |
| commit | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (patch) | |
| tree | 016692552e9880b3e37a715b53f45db707c83a91 /passes/cmds/show.cc | |
| parent | ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff) | |
| download | yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.gz yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.bz2 yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.zip | |
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/cmds/show.cc')
| -rw-r--r-- | passes/cmds/show.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 58acd302d..8b1b43f44 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -555,7 +555,7 @@ struct ShowWorker if (!design->selected_module(module->name)) continue; if (design->selected_whole_module(module->name)) { - if (module->get_bool_attribute("\\blackbox")) { + if (module->get_blackbox_attribute()) { // log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else @@ -771,7 +771,7 @@ struct ShowPass : public Pass { if (format != "ps" && format != "dot") { int modcount = 0; for (auto &mod_it : design->modules_) { - if (mod_it.second->get_bool_attribute("\\blackbox")) + if (mod_it.second->get_blackbox_attribute()) continue; if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) continue; |