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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 14:21:10 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-25 14:21:10 -0700 |
| commit | a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4 (patch) | |
| tree | 7ad89229bedd897e3dc895084a99197dcf04b8a3 /passes/cmds/select.cc | |
| parent | 59b355fb85cb7cda4a25696850bb3caffce3115f (diff) | |
| parent | 08221edbc15333bcd05ae65cee09c86f875076ab (diff) | |
| download | yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.tar.gz yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.tar.bz2 yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.zip | |
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
xilinx: tidy up cells_sim.v a little
Diffstat (limited to 'passes/cmds/select.cc')
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