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author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:08:55 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:27:48 +0200 |
commit | 7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch) | |
tree | 563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/cmds/select.cc | |
parent | d86a25f145012ccb6b2048af3aae22f13b97b505 (diff) | |
download | yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.gz yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.bz2 yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.zip |
Using log_assert() instead of assert()
Diffstat (limited to 'passes/cmds/select.cc')
-rw-r--r-- | passes/cmds/select.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 85c52277c..bbfa396ba 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1120,7 +1120,7 @@ struct SelectPass : public Pass { work_stack.pop_back(); } - assert(design->selection_stack.size() > 0); + log_assert(design->selection_stack.size() > 0); if (clear_mode) { design->selection_stack.back() = RTLIL::Selection(true); |