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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-13 14:55:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-13 14:55:24 +0100 |
| commit | 717abc93a8f6be8ddf36df735a4ce0a1821e5e0e (patch) | |
| tree | 6d8963f79352e8903130c260c175a60535fb7cfb /passes/cmds/select.cc | |
| parent | c9672e2e2eaf410c55145262880d1b0eba372193 (diff) | |
| download | yosys-717abc93a8f6be8ddf36df735a4ce0a1821e5e0e.tar.gz yosys-717abc93a8f6be8ddf36df735a4ce0a1821e5e0e.tar.bz2 yosys-717abc93a8f6be8ddf36df735a4ce0a1821e5e0e.zip | |
Recognize stand-alone obj pattern even when it contains a slash
Diffstat (limited to 'passes/cmds/select.cc')
| -rw-r--r-- | passes/cmds/select.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index ae301040a..a0720797f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -760,6 +760,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!design->selected_active_module.empty()) { arg_mod = design->selected_active_module; arg_memb = arg; + } else + if (GetSize(arg) >= 2 && arg[0] >= 'a' && arg[0] <= 'z' && arg[1] == ':') { + arg_mod = "*", arg_memb = arg; } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { |