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authorAlberto Gonzalez <boqwxp@airmail.cc>2020-04-09 23:55:24 +0000
committerAlberto Gonzalez <boqwxp@airmail.cc>2020-04-16 18:49:55 +0000
commit0424555702de0c17841d8306f734faa788bc504d (patch)
tree0fa20f10fbefc7d97163130e57ef0d09e40d3b61 /passes/cmds/scatter.cc
parent0787af947f92d9d1040623b5d2e8c737c0aee0a9 (diff)
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Replace pseudo-private member access to `connections_` in `passes/cmds/scatter.cc`.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
Diffstat (limited to 'passes/cmds/scatter.cc')
-rw-r--r--passes/cmds/scatter.cc23
1 files changed, 10 insertions, 13 deletions
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 8c95e4289..cd1b3286f 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -48,20 +48,17 @@ struct ScatterPass : public Pass {
for (auto module : design->selected_modules())
{
- for (auto cell : module->cells())
- for (auto &p : cell->connections_)
- {
- RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size());
-
- if (ct.cell_output(cell->type, p.first)) {
- RTLIL::SigSig sigsig(p.second, wire);
- module->connect(sigsig);
- } else {
- RTLIL::SigSig sigsig(wire, p.second);
- module->connect(sigsig);
+ for (auto cell : module->cells()) {
+ std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections;
+ for (auto conn : cell->connections())
+ new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size())));
+ for (auto &it : new_connections) {
+ if (ct.cell_output(cell->type, it.first))
+ module->connect(RTLIL::SigSig(it.second.first, it.second.second));
+ else
+ module->connect(RTLIL::SigSig(it.second.second, it.second.first));
+ cell->setPort(it.first, it.second.second);
}
-
- p.second = wire;
}
}
}