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author | Clifford Wolf <clifford@clifford.at> | 2019-09-24 18:08:59 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-09-24 18:08:59 +0200 |
commit | 6c427d36dd682b97da5f94cd7f0e261ad0802eef (patch) | |
tree | 941bda119fbe3d112819b888e19624b2f6a709d1 /passes/cmds/portlist.cc | |
parent | 057dae4f78ef604964fb12175f5b263bb386da24 (diff) | |
download | yosys-6c427d36dd682b97da5f94cd7f0e261ad0802eef.tar.gz yosys-6c427d36dd682b97da5f94cd7f0e261ad0802eef.tar.bz2 yosys-6c427d36dd682b97da5f94cd7f0e261ad0802eef.zip |
Add "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/cmds/portlist.cc')
-rw-r--r-- | passes/cmds/portlist.cc | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc new file mode 100644 index 000000000..6eedfbbf6 --- /dev/null +++ b/passes/cmds/portlist.cc @@ -0,0 +1,76 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct PortlistPass : public Pass { + PortlistPass() : Pass("portlist", "list (top-level) ports") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" portlist [options] [selection]\n"); + log("\n"); + log("This command lists all module ports found in the selected modules.\n"); + log("\n"); + log("If no selection is provided then it lists the ports on the top module.\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + // if (args[argidx] == "-ltr") { + // config.ltr = true; + // continue; + // } + break; + } + + auto handle_module = [&](RTLIL::Module *module) { + for (auto port : module->ports) { + auto *w = module->wire(port); + log("%s [%d:%d] %s\n", w->port_input ? w->port_output ? "inout" : "input" : "output", + w->upto ? w->start_offset : w->start_offset + w->width - 1, + w->upto ? w->start_offset + w->width - 1 : w->start_offset, + log_id(w)); + } + }; + + if (argidx == args.size()) + { + auto *top = design->top_module(); + if (top == nullptr) + log_error("Can't find top module in current design!\n"); + handle_module(top); + } + else + { + extra_args(args, argidx, design); + for (auto module : design->selected_modules()) + handle_module(module); + } + } +} PortlistPass; + +PRIVATE_NAMESPACE_END |