diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
| commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/connwrappers.cc | |
| parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
| download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip | |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/cmds/connwrappers.cc')
| -rw-r--r-- | passes/cmds/connwrappers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index d7560ab1a..9faeffafa 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -109,7 +109,7 @@ struct ConnwrappersWorker if (!design->selected(module, cell)) continue; - for (auto &conn : cell->connections()) + for (auto &conn : cell->connections_) { std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector(); RTLIL::SigSpec old_sig; |