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| author | George Rennie <georgerennie@gmail.com> | 2022-06-18 18:28:12 +0100 |
|---|---|---|
| committer | George Rennie <georgerennie@gmail.com> | 2022-06-18 18:28:12 +0100 |
| commit | 5dfad5101d92edb484da2e5306cde58b8d958e7d (patch) | |
| tree | 33b9f2a51e28e3286b8e1b58fbbefc867bde6b28 /passes/cmds/chformal.cc | |
| parent | e39c422734219bb0601827cb7c1d081f7ac7817b (diff) | |
| download | yosys-5dfad5101d92edb484da2e5306cde58b8d958e7d.tar.gz yosys-5dfad5101d92edb484da2e5306cde58b8d958e7d.tar.bz2 yosys-5dfad5101d92edb484da2e5306cde58b8d958e7d.zip | |
chformal: Rename -coverprecond to -coverenable
Diffstat (limited to 'passes/cmds/chformal.cc')
| -rw-r--r-- | passes/cmds/chformal.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index c4666f1f0..c3590855b 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -55,8 +55,8 @@ struct ChformalPass : public Pass { log(" -skip <N>\n"); log(" ignore activation of the constraint in the first <N> clock cycles\n"); log("\n"); - log(" -coverprecond\n"); - log(" add a cover statement for the precondition (enable signal) of the cells\n"); + log(" -coverenable\n"); + log(" add cover statements for the enable signals of the constraints\n"); log("\n"); log(" -assert2assume\n"); log(" -assume2assert\n"); @@ -117,7 +117,7 @@ struct ChformalPass : public Pass { mode_arg = atoi(args[++argidx].c_str()); continue; } - if (mode == 0 && args[argidx] == "-coverprecond") { + if (mode == 0 && args[argidx] == "-coverenable") { mode = 'p'; continue; } @@ -273,7 +273,7 @@ struct ChformalPass : public Pass { if (mode =='p') { for (auto cell : constr_cells) - module->addCover(NEW_ID_SUFFIX("coverprecond"), + module->addCover(NEW_ID_SUFFIX("coverenable"), cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); } else |