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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
| commit | 9dc11cd842952deca8e826b662f4565e2b52bd1d (patch) | |
| tree | 6caa919ebcb4618581d8dce4a43f98dbe585bda8 /passes/cmds/add.cc | |
| parent | b25254020c7edc9e4d3fb2a24be5f029a09a1ee0 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.gz yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.bz2 yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index cfccca966..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; |