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| author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
| commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
| tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /passes/cmds/add.cc | |
| parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
| download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip | |
Use C++11 final/override keywords.
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 91f8c2add..a2f4a9100 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n struct AddPass : public Pass { AddPass() : Pass("add", "add objects to the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -150,7 +150,7 @@ struct AddPass : public Pass { log("Add module[s] with the specified name[s].\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::string command; std::string arg_name; |